1. Field of the Invention
The present invention relates to a drive apparatus for a display panel such as a matrix display-type plasma display panel (PDP).
2. Description of the Related Background Art
It is well known that a PDP is a thin, flat display for which various kinds of research have been conducted, and that one kind of PDP is known as a matrix display-type PDP.
FIG. 1 shows a schematic configuration of a PDP drive apparatus having the PDP.
As shown in FIG. 1, a PDP 1 has row electrodes Y1 to Ynk and row electrodes X1 to Xnk forming row electrode pairs such that each X and Y pair corresponds to each row (row 1 to row nk) of a single screen. The PDP 1 additionally comprises column electrodes D1 to Dm constituting column electrodes that correspond to each column (column 1 to column m) of a single screen. The column electrodes D1 to Dm are formed orthogonally to the row electrode pairs with dielectric layers and a discharge gap, which are not shown in the figure, interposed therebetween. A discharge cell that corresponds to a single pixel is formed at the intersection of one row electrode pair and one column electrode.
The row electrodes X1 to Xnk and row electrodes Y1 to Ynk are each divided into n groups of k rows per group. Specifically, these groups are X1 to Xk, Xk+1 to X2k, . . . , X(n−1)k+1 to Xnk and Y1 to Yk, Yk+1 to Y2k, . . . , Y(n−1)k+1 to Ynk These n groups correspond to X row electrode drivers 31 to 3n and Y row electrode drivers 41 to 4n, respectively.
A address driver 2 converts pixel data of each pixel based on a video signal to a pixel data pulse having a voltage value corresponding to a logic level of the pixel data and applies the voltage to each of the column electrodes D1 to Dm for each row.
The X row electrode drivers 31 to 3n, respectively, have sustaining, drivers 51 to 5n and output drivers 61 to 6n. There is a line XL commonly connecting between sustaining drivers 51 to 5n and output drivers 61 to 6n. Each of the sustaining drivers 51 to 5n generates, as a drive pulse, a reset pulse for initializing residual wall charge of each discharge cell and a sustaining discharge pulse for sustaining a discharge luminescence state of a luminescent discharge cell as described later, and applies these pulses to the row electrodes X1 to Xnk via the corresponding output driver 61 to 6n.
The Y row electrode drivers 41 to 4n, respectively, have sustaining drivers 71 to 7n and scan drivers 81 to 8n. There is a line YL commonly connecting between the sustaining drivers 71 to 7n and the scan drivers 81 to 8n. Each of the sustaining drivers 71 to 7n, in a manner similar to the sustaining drivers 51 to 5n of the X row electrode drivers 31 to 3n, generates a reset pulse for initializing residual wall charge of each discharge cell and a sustaining discharge pulse for sustaining a discharge luminescence state of each luminescent discharge cell, and applies these pulses on each of the row electrodes Y1 to Ynk via the corresponding scan driver 81 to 8n. Each of the scan drivers 81 to 8n generates a scan pulse SP for setting a luminescent discharge cell or non-luminescent discharge cell by obtaining the charge corresponding to the pixel data pulse for each discharge cell, and applies the pulse to the row electrodes Y1 to Ynk.
The connecting lines XL and YL are provided to unify the voltage levels of the drive pulses for the drivers 31 to 3n, 41 to 4n, respectively.
A control circuit 9 controls generation timing of the drive pulses of sustaining drivers 51 to 5n, output drivers 61 to 6n, the sustaining drivers 71 to 7n, and the scan drivers 81 to 8n.
FIG. 2 shows the configurations of the sustaining driver 71 and the scan driver 81. The sustaining driver 71 has power supplies B1, B2, a capacitor C, coils L1 to L2, a resistor R1, diodes D1, D2, and switching elements S1 to S6. The power supply B1 outputs a voltage VR. The power supply B2 outputs a voltage VS. The negative terminal of the power supply B1 is grounded, and the positive terminal is connected to the above-mentioned connecting line YL via the switching element S6 and the resistor R1.
The connecting line YL is grounded via the switching element S5 and the switching element S4. The voltage VS from the positive terminal of the power supply B2 is applied via the switching element S3 to a connecting line CL between the switching element S5 and the switching element S4. Between the connecting line CL and the ground, the switching element S1, the diode D1, the coil L1, and the capacitor C are connected in series sequentially from the connecting line CL side. The polarity of the diode D1 is such that the anode is the coil L1 side and the cathode is the switching element S1 side. The series circuit including the coil L2, diode D2, and switching element S2 is connected in parallel to the series portion including the switching element S1, diode D1, and coil L1. One end of the coil L2 is connected to the connecting line CL, and one end of the switching element S2 is connected to the capacitor C. The polarity of the diode D2 is such that the anode is the coil L2 side and the cathode is the switching element S2 side.
The scan driver 81 has a power supply B3, switching elements S71 to S7k, S81 to S8k, and diodes D71 to D7k, D81 to D8k. The power supply B3 outputs a voltage Vh. The positive terminal of the power supply B3 is connected to the connecting line YL, and the negative terminal is connected to a negative-side connecting line NL within the scan driver 81. Between the connecting line YL and the negative-side connecting line NL, the switching elements S71 and S81 are connected in series, and the diodes D71 and D81 are also connected in series. The polarities of the diodes D71 and D81 are such that the cathode of the diode D71 is the connecting line YL side, the anode of the diode D71 and the cathode of the diode D81 are connected with each other, and the anode of diode D81 is the connecting line NL side. In addition, the connection point between the switching elements S71 and S81 and the connection point between the diodes D71 and D81 are connected with each other, and the connecting line between these connection points is connected to the row electrode Y1. Also, the switching elements S72, S82, diodes D72, D82, and row electrode Y2, . . . , the switching elements S7k, S8k, diodes D7k, D8k, and row electrode Yk are each connected in the same way as the switching elements S71, S81, diodes D71, D81, and row electrode Y1.
The switching elements S1 to S6, S71 to S7k, and S81 to S8k are respectively switched in response to control signals supplied from a control circuit 9.
The sustaining drivers 72 to 7n and the sustaining drivers 51 to 5n of the X row electrode drivers 31 to 3n are also provided with the same configuration as the sustaining driver 71. However, for the sustaining drivers 51 to 5n of the X row electrode drivers 31 to 3n, the power supply B1 is connected with the reverse polarity of that for the sustaining drivers 71 to 7n. In addition, the scan drivers 82 to 8n and the output drivers 61 to 6n of the X row electrode drivers 31 to 3n are also provided with the same configuration as the scan driver 81.
An operation of the PDP drive apparatus having the configuration as mentioned above, and more particularly, of the sustaining driver 71 and scan driver 81, will be explained next with reference to a timing chart in FIG. 3. The operation of the PDP drive apparatus has a reset period, an address period, and a sustaining period.
First, when a reset period starts, the sustaining drivers 51 to 5n of the X row electrode drivers 31 to 3n and the sustaining drivers 71 to 7n of the Y row electrode drivers 41 to 4n each generate reset pulses. The reset pulses are applied simultaneously to the row electrodes X1 to Xnk and row electrodes Y1 to Ynk. FIG. 3 shows a negative reset pulse that is applied to the row electrode X1 and a positive reset pulse that is applied to the row electrode Y1.
In the sustaining driver 71 and the scan driver 81, the operation during the reset period is as follows. In the sustaining driver 71, the switching element S6 is turned on, and the switching elements S1 to S5 are turned off. In the scan driver 81, the switching elements S71 to S7k are turned on, and the switching elements S81 to S8k are turned off. As a result, a current flows from the positive terminal of the power supply B1 to the row electrodes Y1 to Yk via the resistor R1, connecting line YL, and switching elements S71 to S7k, voltages that are applied to the row electrodes Y1 to Yk gradually increase due to the capacitance components between the row electrodes X1 to Xk and Y1 to Yk, and positive reset pulses are formed as shown in FIG. 3. The voltage of these reset pulses finally increases to a voltage VR. At this time, the switching elements S4 and S5 are turned on and the switching element S6 are turned off. Thus, since the connecting line YL is grounded, the reset pulses disappear.
As a result of the simultaneous applications of these reset pulses to the row electrodes X1 to Xnk and row electrodes Y1 to Ynk, all the discharge cells of the PDP 1 really discharge, and charged particles are generated. After the discharge ends, wall charges of predetermined amounts are uniformly formed on dielectric layers of all the discharge cells.
After the reset pulses have disappeared, an address period starts. During the address period, the address driver 2 converts pixel data for each pixel based on a video signal to pixel data pulses DP1 to DPm having voltage values corresponding to logic levels of the pixel data, and applies these voltages sequentially to the column electrodes D1 to Dm for each row. The pixel data pulses DP1 to DPm are applied for the row electrode Y1 as shown in FIG. 3. A scan pulse is repeatedly applied to the row electrodes Y1 to Ynk in that order by the scan drivers 81 to 8n in synchronism with the individual application timing of the pixel data pulses DP1 to DPm.
In the scan driver 81, the operation during the address period will be explained as follows. First, the switching element S71 is turned off and the switching element S81 is turned on at the same time. As a result, a voltage −Vh by the power supply B3 is added to the row electrode Y1, as shown in FIG. 3, to become a scan pulse. The ground potential of 0V is applied to the row electrode X1 as shown in FIG. 3. After the switching element S71 has been turned on and the switching element S81 has been turned off at the same time, the switching element S72 is turned off and the switching element S82 is turned on at the same time, and then the scan pulse is added to the row electrode Y2. In this manner, the scan pulse is applied sequentially to the row electrodes Y1 to Yk.
Of discharge cells belonging to a row electrode to which a scan pulse is applied, discharges will occur at discharge cells to which positive voltage pixel data pulses are respectively applied at the same time, and most of the wall charge as mentioned above is lost for each of the discharged cells. Since no discharge occurs at the remaining discharge cells to which a scan pulse is applied but no positive voltage pixel data pulse is applied, each wall charge remains. The discharge cells each of which has the wall charge are luminous discharge cells, and the discharged cells each of which has no wall charge are non-luminous discharge cells.
When a sustaining period starts after the address period, the X row electrode drivers 31 to 3n apply a positive voltage sustaining pulse IPX to the electrodes X1 to Xnk, and when sustaining pulse IPX is eliminated, the Y row electrode drivers 41 to 4n apply a sustaining pulse IPY to the electrodes Y1 to Ynk. The application of the sustaining pulse IPX to the electrodes X1 to Xnk alternates with the application of the sustaining pulse IPY to the electrodes Y1 to Ynk. Since luminous discharge cells each of which has the wall charge remained repeatedly emit, these cells maintain a luminous state.
In the sustaining driver 71, the switching element S1 is turned on and the switching element S4 is turned off during the sustain period. The potential of the electrode Y1 is substantially equal to the ground potential of 0V when the switching element S4 is turned on. However, when the switching element S4 is turned off and the switching element S1 is turned on, a current flows to the row element Y1 via the coil L1, diode D1, switching element S1, switching element S5, connecting line YL, and switching element S71 due to a charge stored in the capacitor C, and charges the capacitance component between the row electrodes Y1 and X1. At this time, the potential of the electrode Y1 increases gradually as shown in FIG. 3 due to the time constant of the coil L2 and capacitance component.
Subsequently, the switching element S1 is turned off and the switching element S3 is turned on. As a result, the voltage VS by the power supply B2 is applied to the row electrode Y1 via the switching element S3, switching element S5, connecting line YL, and switching element S71. After that, the switching element S3 is turned off and the switching element S2 is turned on, and a current flows into the capacitor C via the diode D71, connecting line YL, switching element S5, coil L2, diode D2, and switching element S2 from the electrode Y1 due to the charge stored in the capacitance component between the row electrodes Y1 and X1. At this time, the potential of the electrode Y1 decreases gradually as shown in FIG. 3 due to the time constant of the coil L2 and capacitor C. When the potential of the row electrode Y1 is substantially equal to 0V, the switching element S2 is turned off and the switching element S4 is turned on. The row electrode Y1 is supplied with the sustaining pulse IPY of a positive voltage as shown in FIG. 3, according to the operation.
The row electrodes X1 to Xnk and row electrodes Y1 to Ynk are each divided into n groups having k rows per group, and the X row electrode driver and Y row electrode driver are provided for each row electrode group as described above. The configuration is done to reduce a load for a single driver and distribute the overall generation of heat to each driver.
However, since the switching elements such as FETs, which respond to control signals, have different response speeds from each other in each of the X row electrode drivers and Y row electrode drivers, there are temporal errors in the generation of drive pulses in the row electrode drivers. The temporal errors in the generation of drive pulses cause the following problem. A load is applied to a row electrode driver at which a drive pulse is early generated due to the existence of the connecting line between the row electrode drivers, and the value of an electric current supplied to the row electrode from that row electrode driver increases. Thus, the loaded row electrode driver generates heat. For example, if some delay interval elapses after the Y row electrode driver 41 starts outputting a sustaining pulse as shown in FIG. 4A before the Y row electrode driver 42 outputs a sustaining pulse as shown in FIG. 4B, the output current by the drive pulse of the Y row electrode driver 41 shown in FIG. 4C becomes larger than the output current by the drive pulse of the Y row electrode driver 42 shown in FIG. 4D, and the amount of heat generated by the Y row electrode driver 41 increases.